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ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue sep.5.2006 rev. 1.1 revised package outline dimension(tsop-ii) a pr.12.2007 rev. 2.0 revised i cc and i sb1 revised test condition of i sb1 /i dr added e and i grade revised absolute maximun ratings jun.23.2007 rev. 2.1 a dding pkg type : 36-ball 6mm x 8mm tfbg a revised test condition of i cc mar.31.2008 rev. 2.2 revised features & ordering information lead free and green package available to green package available deleted t solder in absolute maximun ratings added packing type in ordering information a pr.17.2009 rev. 2.3 rev. 2.4 revised package outline dimension in page 9/10/12 revised ordering information in page 13 ma y .7.2010 aug.25.2010
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 10/12/15/20/25ns ? very low power consumption: operating current(normal version): 180/160/140/80/70ma(max.) standby current: 12ma(max. for 10/12/15ns) 5ma(max. for 20/25ns) 100 a( (max. for 20/25ns ll version) ? single 3.3v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data retention voltage : 2.0v (min.) ? green package available ? package : 32-pin 8mm x 20mm tsop-i 32-pin 8mm x 13.4mm stsop 44-pin 400 mil tsop-ii 36-ball 6mm x 8mm tfbga general description the ly61l5128 is a 4,194,304-bit low power cmos static random access memory organized as 524,288 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly61l5128 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. the ly61l5128 operates from a single power supply of 3.3v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, max.) operating(icc,max.) ly61l5128 0 ~ 70 3.15/3.0 ~ 3.6v 10/12/15 ns 12ma 180/160/140ma ly61l5128(e) -20 ~ 80 3.15/3.0 ~ 3.6v 10/12/15 ns 12ma 180/160/140ma ly61l5128(i) -40 ~ 85 3.15/3.0 ~ 3.6v 10/12/15 ns 12ma 180/160/140ma ly61l5128 0 ~ 70 3.0 ~ 3.6v 20/25ns 5ma 80/70ma ly61l5128(e) -20 ~ 80 3.0 ~ 3.6v 20/25ns 5ma 80/70ma ly61l5128(i) -40 ~ 85 3.0 ~ 3.6v 20/25ns 5ma 80/70ma ly61l5128(ll) 0 ~ 70 3.0 ~ 3.6v 20/25ns 100a 80/70ma ly61l5128(lle) -20 ~ 80 3.0 ~ 3.6v 20/25ns 100a 80/70ma ly61l5128(lli) -40 ~ 85 3.0 ~ 3.6v 20/25ns 100a 80/70ma
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? functional block diagram decoder i/o data circuit control circuit 512kx8 memory array column i/o a0-a18 vcc vss dq0-dq7 ce# we# oe# pin description symbol description a0 - a18 address inputs dq0 ? dq7 data inputs/outputs ce# chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? pin configuration ly61l5128 a3 a4 nc nc a8 a0 ce# dq0 vcc vss nc a16 oe# dq6 dq7 dq5 vss vcc dq4 a9 dq1 dq2 tsop-ii 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a15 a2 we# a18 nc nc nc a12 a13 dq3 a10 a14 nc nc nc a11 34 29 30 31 32 33 44 39 40 41 42 43 35 36 37 38 nc a1 a17 a7 a6 a5 tfbga oe# we# a12 a11 a13 nc a18 a10 a14 a15 dq5 dq6 dq7 a9 vss a8 a16 dq4 vcc vcc dq3 a17 vss a7 a0 dq2 dq1 dq0 a6 a1 a3 a5 nc a4 a2 123456 h g c d e f a b ce# tsop-i/stsop dq3 a11 a9 a8 a13 dq2 a10 a14 a12 a7 a6 a5 vcc dq7 dq6 dq5 dq4 vss dq1 dq0 a0 a1 a2 a4 a3 ly61l5128 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# a17 a15 a16 a18 32 31 29 30
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 4.6 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -20 to 80(e grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce# oe# we# i/o operation supply current standb y h x x high-z i sb1 output disable l h h high-z i cc read l l h d out i cc write l x l d in i cc note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 10/12 3.15 3.3 3.6 v 15/20/25 3.0 3.3 3.6 v input high voltage v ih *1 2.2 - v cc +0.3 v input low voltage v il *2 - 0.3 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -4m a 2.4 - - v output low voltage v ol i ol = 8m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il , i i/o = 0ma others at v ih or v il 10 - - 180 m a 12 - - 160 m a 15 - - 140 m a 20 - 50 80 m a 25 - 45 70 m a standby power supply current i sb1 ce# v R cc - 0.2v, others at 0.2v or v cc - 0.2v 10/12/15 - - 12 m a 20/25 - 0.5 5* 5 ma 20/25ll - 20 100* 6 a
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 5. 1ma for special request 6. 50 a for special request capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -8ma/16m a ac electrical characteristics (1) read cycle parameter sym. ly61l5128 -10 ly61l5128 -12 ly61l5128 -15 ly61l5128 -20 ly61l5128 -25 unit min. max. min. max. min. max. min. max. min. max. read cycle time t rc 10 - 12 - 15 - 20 - 25 - ns address access time t aa - 10 - 12 - 15 - 20 - 25 ns chip enable access time t ace - 10 - 12 - 15 - 20 - 25 ns output enable access time t oe - 5-6-7-8 - 9ns chip enable to output in lo w -z t clz * 2 -3-4-4- 4 -ns output enable to output in lo w -z t olz * 0 -0-0-0- 0 -ns chip disable to output in high-z t chz * - 5-6-7-8 - 9ns output disable to output in high-z t ohz * - 5-6-7-8 - 9ns output hold from address change t oh 3 -3-3-3- 3 -ns (2) write cycle parameter sym. ly61l5128 -10 ly61l5128 -12 ly61l5128 -15 ly61l5128 -20 ly61l5128 -25 unit min. max. min. max. min. max. min. max. min. max. write cycle time t wc 10 - 12 - 15 - 20 - 25 - ns address valid to end of write t aw 8 - 10 - 12 - 16 - 20 - ns chip enable to end of write t cw 8 - 10 - 12 - 16 - 20 - ns address set-up time t as 0 -0-0-0- 0 -ns write pulse width t wp 8 - 9 - 10 - 11 - 12 - ns write recovery time t wr 0 -0-0-0- 0 -ns data to write time overlap t dw 6 -7-8-9- 10 -ns data hold from end of write time t dh 0 -0-0-0- 0 -ns output active from end of write t ow * 2 -3-4-5- 6 -ns write to output in high-z t whz * - 6 - 7 - 8 - 9 - 10 ns *these parameters are guaranteed by device characterization, but not production tested.
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid t oh oe# t ace ce# t aa address t rc high-z high-z t clz t olz t oe t chz t ohz notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low . 3.address must be valid prior to or coincident with ce# = low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc (4) t ow write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc notes : 1.we#, ce# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance stat e. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? data retention characteristics parameter symbol test cond ition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 2.0 - 3.6 v data retention current i dr v cc = 2.0v ce# v R cc - 0.2v others at 0.2v or v cc - 0.2v 10/12/15 - - ma 20/25 - 0.5 1 ma 20/25ll - 10 50 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform vcc ce# v dr R 2.0v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? package outline dimension 32 pin 8mm x 20mm tsop-i package outline dimension unit sym. inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.155 0.055 d 0.724 0.008 18.40 0.20 e 0.315 0.008 8.00 0.20 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0.024 0.004 0.60 0.10 l1 0.0315 0.004 0.08 0.10 y 0.003 (max) 0.08 (max) 0 o 5 o 0 o 5 o
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? 32 pin 8mm x 13.4mm stsop package outline dimension 1 16 17 32 c l hd d "a" e e 12 (2x) 12 (2x) seating plane y 32 17 16 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 b unit sym. inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.155 0.055 d 0.465 0.008 11.80 0.20 e 0.315 0.008 8.00 0.20 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.02 0.008 0.50 0.20 l1 0.031 0.005 0.8 0.125 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? 44-pin 400mil tsop- package outline dimension symbols dimensions in millmeters dimensions in mils min. nom. max. min. nom. max. a - - 1.20 - - 47.2 a1 0.05 0.10 0. 15 2.0 3.9 5.9 a2 0.95 1.00 1. 05 37.4 39.4 41.3 b 0.30 - 0.45 11.8 - 17.7 c 0.12 - 0.21 4.7 - 8.3 d 18.212 18.415 18.618 717 725 733 e 11.506 11.760 12.014 453 463 473 e1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5 - l 0.40 0.50 0. 60 15.7 19.7 23.6 zd - 0.805 - - 31.7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? 36 ball 6mm 8mm tfbga package outline dimension
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 13 ? ordering information
ly61l5128 rev. 2.4 512k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 14 ? this page is left blank intentionally.

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